SEMICONDUCTOR OFFICE CAMPUS
The masterplan for this campus called for phased implementation of 1M sf of office space in three buildings, 750,000 sf of computer assembly space in two buildings, and 6,000 parking spaces with 70% of all stalls located within 700 feet of a building entrance.
Phase 1 was a design-build fast-track project consisting of: DP1, a 370,000 sf computer assembly plant with development labs; DP2, a 4-story, 325,000 sf office building, with a 25,000 sf cafeteria and computer room; and 2,100 parking spaces. Site development included an Open Area Test Site (OATS) facility, sports courts, and loading docks for shipping and receiving.
Phase 2 was a design-build fast-track project for DP3, a second 4-story 325,000 sf office with a computer room and additional parking.
Richard Harper, Principal-in-Charge, English Harper Reta Architects